The EPMATCN is an EEPROM Complex Programmable Logic Device with usable gates and 64 macro cells. MAX A CPLD is a. The EPMATCN is an EEPROM Complex Programmable Logic Device IC with usable gates and 32 macro cells. MAX A CPLD is a. Altera has a free FPGA and CPLD development package called Quartus II Web Edition. This is the only development tool we’re aware of.

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It is possible to create you own logical circuits and emulate real hardware chips on the lowest level.

It has a programming capacity of 64 macrocells. A macrocell is the smallest programmable part inside a CPLD. Certainly enough to create a blinking led. We will be using Quartus II The correct version is important, as it needs to support our MAX device. In this blog I will not cover how to do a full set up or this JTAG programmer, there are plenty of tutorials online.

I will only focus on the block diagram and the VHDL code to blink the led. First we will need to create a new project in Quartus. This can be done by selecting the New Project Wizard in File menu.

Specify the directory for your project and the name. In the Name filter you need to type in: You will see that this device is powered by 3.


Click on Finish and your project will be created. Double click on the canvas and this will pop-up a dialog where you can insert a input and a output pin.

Altera MAX 3000A

This is how it will look after you have completed the step above. The program should already suggest that name.

Note that it is important to name this file the same as your project, otherwise you will get compiling errors. Now create a new file and this time select VHDL file.

MAX 3000A Device Family Technical Information & Support

You will get an empty editor window. Paste in the code from below and save the file again as something like clock. The variable tick will determine how fast your led will blink. Now switch to Files tab next to the Hierarchy tab in the Project Navigator window and right click on the clock. This step is important as it will altrra you te add a block diagram of our created clock. Insert it in your block diagram by clicking OK. Just like in the screenshot below.

Now start the compilation of the project. Save any changes if prompted. The compilation should be succesful with some warnings that can be safely ignored. You can also see that we have used 6 of 34 pins. You may think that this is not true, because we have only used 2. But actually the 4 other pins are reserved for the JTAG programmer. Now it’s time to open the Pin Planner dialog and assign the input and output pins from to physical mwx on the chip.


MAX A Device Family Technical Information & Support

Now we are going to connect our board to the JTAG programmer and power supply. The JTAG cable does not supply power so we need to provide it from an external source.

Without power the board will not program. I am using this breadboard power supply which has 3. On the CPLD board supply the power to those 2 pins in the corner. I have used a multimeter to pinpoint the correct ones.

Blinking LED with Altera EPM CPLD

I could not prick in into the breadboard, because the DIP spacing is different 2. It is time to finilize our project. First we will re-compile it and then go the Programmer dialog, which is located in Tools menu. In this dialog make sure that you have selected the correct JTAG programmer. In my case it is USB-Blaster. If you have any questions don’t hesitate to contact me.